| Presentation | 2008-01-17 Memory Binding and Scheduling in High Level Synthesis for FPGAs Yuki SAGAWA, Tsuyoshi SADAKATA, Yusuke MATSUNAGA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In High Level Synthesis for FPGAs, arrays in behavioral description may be bound to the same memory block since the number of memory block is fixed for FPGAs. The number of access to such arrays at one step is limited to the number of memory port. If arrays that are accessed frequently are bound to the same memory block, array accessess will conflict with each other and the conflict will affect the number of steps. Therefore, memory binding and scheduling should be considered simultaneously. In this paper, we propose a heuristic algorithm that deals with memory binding and scheduling simultaneously under the memory size, the number of memory, and the number of memory port constraints subject to minimize the sum of maximum step for all Data Flow Graphs. Experimental results show that the proposed algorithm can find as a good solution as the approach using Simulated Annealing in many cases. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Level Synthesis / Memory Binding / Scheduling FPGA |
| Paper # | VLD2007-120,CPSY2007-63,RECONF2007-66 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Memory Binding and Scheduling in High Level Synthesis for FPGAs |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis |
| Keyword(2) | Memory Binding |
| Keyword(3) | Scheduling FPGA |
| 1st Author's Name | Yuki SAGAWA |
| 1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Tsuyoshi SADAKATA |
| 2nd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| 3rd Author's Name | Yusuke MATSUNAGA |
| 3rd Author's Affiliation | Faculty School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2008-01-17 |
| Paper # | VLD2007-120,CPSY2007-63,RECONF2007-66 |
| Volume (vol) | vol.107 |
| Number (no) | 419 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |