| Presentation | 2008-01-17 A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed-Register Architectures Tetsuya ENDO, Akira OHCHI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As device feature size decreases, interconnection delay becomes the dominating factor of total delay. In addition, as the number of total gates and the number of wirings in each unit area increase, the number of multiplexers that is necessary for the wiring control increases. By using a distributed-register architecture, we can synthesize circuits with register-to-register data transfer, and can reduce influence of interconnection delay. However, as the number of wirings required for the connection between registers increases, the needed number of multiplexers is also increased. In this paper, we propose a multiplexer reduction algorithm in high-level synthesis for distributed-register architectures. This algorithm can reduce the number of multiplexers for each functional unit, wiring connection between local registers by optimizing a port re-assignment. We show effectiveness of the proposed algorithm thorough experimental results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multiplexer / high-level synthesis / distributed-register architecture / port assignment / interconnect delay / the number of wirings |
| Paper # | VLD2007-119,CPSY2007-62,RECONF2007-65 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed-Register Architectures |
| Sub Title (in English) | |
| Keyword(1) | multiplexer |
| Keyword(2) | high-level synthesis |
| Keyword(3) | distributed-register architecture |
| Keyword(4) | port assignment |
| Keyword(5) | interconnect delay |
| Keyword(6) | the number of wirings |
| 1st Author's Name | Tetsuya ENDO |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Akira OHCHI |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2008-01-17 |
| Paper # | VLD2007-119,CPSY2007-62,RECONF2007-65 |
| Volume (vol) | vol.107 |
| Number (no) | 419 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |