Presentation | 2008-01-16 Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating Toshiaki SHIRAI, Toshihiro KASHIMA, Seidai TAKEDA, Mitsutaka NAKATA, Kimiyoshi USAMI, Yohei HASEGAWA, Naomi SEKI, Hideharu AMANO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Run Time Power Gating(RTPG) is a technology that reduces leakage power in a temporally/spatially fine-grained manner.This paper describes a physical design to apply RTPG to ALU, SHIFT, MULT, DIV, exception handling Coprocessor in a MIPS R3000 processor. Simulation results show that break even point to gain in power savings is 2-32 clock cycles at high temperature in 90nm technology. Delay time of ALU is increased by 16-42% by applying RTPG. Wakeup times of power-gated units are 5ns or less. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | MTCMOS circuits / Power Gating / Leakage Power / Power Dissipation |
Paper # | VLD2007-112,CPSY2007-55,RECONF2007-58 |
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Conference Information | |
Committee | RECONF |
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Conference Date | 2008/1/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating |
Sub Title (in English) | |
Keyword(1) | MTCMOS circuits |
Keyword(2) | Power Gating |
Keyword(3) | Leakage Power |
Keyword(4) | Power Dissipation |
1st Author's Name | Toshiaki SHIRAI |
1st Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology() |
2nd Author's Name | Toshihiro KASHIMA |
2nd Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
3rd Author's Name | Seidai TAKEDA |
3rd Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
4th Author's Name | Mitsutaka NAKATA |
4th Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
5th Author's Name | Kimiyoshi USAMI |
5th Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
6th Author's Name | Yohei HASEGAWA |
6th Author's Affiliation | Department of Information and Computer Science, Keio University |
7th Author's Name | Naomi SEKI |
7th Author's Affiliation | Department of Information and Computer Science, Keio University |
8th Author's Name | Hideharu AMANO |
8th Author's Affiliation | Department of Information and Computer Science, Keio University |
Date | 2008-01-16 |
Paper # | VLD2007-112,CPSY2007-55,RECONF2007-58 |
Volume (vol) | vol.107 |
Number (no) | 418 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |