| Presentation | 2008-01-16 Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka NAKATA, Toshiaki SHIRAI, Toshihiro KASHIMA, Seidai TAKEDA, Kimiyoshi USAMI, Naomi SEKI, Yohei HASEGAWA, Hideharu AMANO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When applying Run-Time Power Gating(RTPG) to a design, logic verification is one of the major problems. Gate-level simulation cannot be carried out in the conventional verification environment because logic netlist includes power switch cells. In this paper, we propose logic modeling for a power switch and simulation methodology for power-gated circuits. In addition, we present about power estimation technique based on the proposed simulation methodology and the novel macro-modeling. Evaluation at ALU with RTPG showed that the accuracy of the estimated power was within 10% against the transistor-level simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MTCMOS circuits / Power Gating / Power Dissipation / Development of verification |
| Paper # | VLD2007-111,CPSY2007-54,RECONF2007-57 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of verification and power estimation methodology for circuits with Run Time Power Gating |
| Sub Title (in English) | |
| Keyword(1) | MTCMOS circuits |
| Keyword(2) | Power Gating |
| Keyword(3) | Power Dissipation |
| Keyword(4) | Development of verification |
| 1st Author's Name | Mitsutaka NAKATA |
| 1st Author's Affiliation | Shibaura Institute of Technology() |
| 2nd Author's Name | Toshiaki SHIRAI |
| 2nd Author's Affiliation | Shibaura Institute of Technology |
| 3rd Author's Name | Toshihiro KASHIMA |
| 3rd Author's Affiliation | Shibaura Institute of Technology |
| 4th Author's Name | Seidai TAKEDA |
| 4th Author's Affiliation | Shibaura Institute of Technology |
| 5th Author's Name | Kimiyoshi USAMI |
| 5th Author's Affiliation | Shibaura Institute of Technology |
| 6th Author's Name | Naomi SEKI |
| 6th Author's Affiliation | Keio University |
| 7th Author's Name | Yohei HASEGAWA |
| 7th Author's Affiliation | Keio University |
| 8th Author's Name | Hideharu AMANO |
| 8th Author's Affiliation | Keio University |
| Date | 2008-01-16 |
| Paper # | VLD2007-111,CPSY2007-54,RECONF2007-57 |
| Volume (vol) | vol.107 |
| Number (no) | 418 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |