| Presentation | 2008-01-16 Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs Yuzo NISHIOKA, Masahiro IIDA, Toshinori SUEYOSHI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In deep sub-micron process, the wire delay exceeds the switching delay. The wire delay is dominant in the total delay. FPGA receicves a benefit by using new process technologies. However, the problem of the wiring delay is influential more than it. FPGA device has a lot of wire make matter worse. For these reasons, performance advances is obstructed in FPGA. In order to solve it, we propose a new routing structure which apply the Small-World Network to FPGA routing structure. It reduces the wire delay by adding a few random wires to regular routing structure. Our routing structure achieved the reduction of the delay in the architecture without cluster based FPGAs before now. In this paper, we evaluate our routing structure for cluster based FPGA. As a result, our routing structure also reduced the critical path delay for some circuits which can expect an improvement in cluster based FPGAs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Wire delay / Routing Structure / Small-World Network |
| Paper # | VLD2007-108,CPSY2007-51,RECONF2007-54 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2008/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Wire delay |
| Keyword(3) | Routing Structure |
| Keyword(4) | Small-World Network |
| 1st Author's Name | Yuzo NISHIOKA |
| 1st Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Masahiro IIDA |
| 2nd Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University |
| 3rd Author's Name | Toshinori SUEYOSHI |
| 3rd Author's Affiliation | Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University |
| Date | 2008-01-16 |
| Paper # | VLD2007-108,CPSY2007-51,RECONF2007-54 |
| Volume (vol) | vol.107 |
| Number (no) | 418 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |