| Presentation | 2008-01-18 A Package-on-Package using Coreless Substrate with Excellent Power Integrity : The electrical characteristics of MLTS and the novel PoP structure Kentaro Mori, Jun Sakai, Katsumi Kikuchi, Shinji Watanabe, Tomoo Murakami, Shintaro Yamamichi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have successfully developed a novel Package-on-Package (PoP) technology for achieving small package thickness and low package warpage. The novel package structure is based on an ultra-thin coreless substrate, called a Multi-Layer Thin Substrate (MLTS). MLTS has considerable advantages over a conventional build-up PWB, especially for operation in the GHz range. The MLTS is fabricated by completely removing the Cu base plate after forming a high-density build-up structure on the base plate. In this paper, however, the Cu posts of 0.5 mm pitch and 125 μm height are formed by selective wet etching of the Cu base plate. If the MLTS has built-in Cu posts as external terminals, the overall substrate can be molded with an appropriate resin for the peripheral area as well as the chip mounting area. Therefore, the novel package can be expected to realize low warpage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Package-on-Package (PoP) / Coreless Substrate / Cu post / Signal Integrity / Power Integrity |
| Paper # | CPM2007-143,ICD2007-154 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2008/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Package-on-Package using Coreless Substrate with Excellent Power Integrity : The electrical characteristics of MLTS and the novel PoP structure |
| Sub Title (in English) | |
| Keyword(1) | Package-on-Package (PoP) |
| Keyword(2) | Coreless Substrate |
| Keyword(3) | Cu post |
| Keyword(4) | Signal Integrity |
| Keyword(5) | Power Integrity |
| 1st Author's Name | Kentaro Mori |
| 1st Author's Affiliation | NEC Corporation() |
| 2nd Author's Name | Jun Sakai |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Katsumi Kikuchi |
| 3rd Author's Affiliation | NEC Corporation |
| 4th Author's Name | Shinji Watanabe |
| 4th Author's Affiliation | NEC Corporation |
| 5th Author's Name | Tomoo Murakami |
| 5th Author's Affiliation | NEC Corporation |
| 6th Author's Name | Shintaro Yamamichi |
| 6th Author's Affiliation | NEC Corporation |
| Date | 2008-01-18 |
| Paper # | CPM2007-143,ICD2007-154 |
| Volume (vol) | vol.107 |
| Number (no) | 426 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |