Presentation 2008-01-18
A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board That Simulates an Actual Memory Module
Yutaka UEMATSU, Hideki OSAKA, Yoji NISHIO, Susumu HATANO,
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Abstract(in English) Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have inserted a low pass filter (LPF) in the Vref line of DRAM chip. To demonstrate this LPF effect, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because of the LPF consisted in the test chip.
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Keyword(in English) DDR-SDRAM / Vref / Noise Tolerance / Noise Sensitivity Measurement / Target Impedance
Paper # CPM2007-139,ICD2007-150
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Conference Date 2008/1/10(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board That Simulates an Actual Memory Module
Sub Title (in English)
Keyword(1) DDR-SDRAM
Keyword(2) Vref
Keyword(3) Noise Tolerance
Keyword(4) Noise Sensitivity Measurement
Keyword(5) Target Impedance
1st Author's Name Yutaka UEMATSU
1st Author's Affiliation Central Research Laboratory, Hitachi, Ltd.()
2nd Author's Name Hideki OSAKA
2nd Author's Affiliation Central Research Laboratory, Hitachi, Ltd.
3rd Author's Name Yoji NISHIO
3rd Author's Affiliation Elpida Memory, Inc.
4th Author's Name Susumu HATANO
4th Author's Affiliation Elpida Memory, Inc.
Date 2008-01-18
Paper # CPM2007-139,ICD2007-150
Volume (vol) vol.107
Number (no) 426
Page pp.pp.-
#Pages 5
Date of Issue