Presentation 2008-01-17
On-Chip Monitoring Technique and Evaluation of Power-Supply Integrity
Makoto NAGATA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) On-Chip monitoring techniques has been applied for detailed understanding of power-supply, ground, as well as substrate noises in a practical LSI chips, in terms of noise generation as well as noise impact on circuit operation. This article introduces a compact noise monitor circuit that can be buried into digital integrated circuits operation. This article introduces a compact noise monitor circuit that can be buried into digital integrated circuits and also on-chip multi-channel monitor system that can probe noise and signals at a variety of points ditributed in a LSI chip. Power-supply integrity measurements demonstrated include dynamic noise inside a processor during its operation and also electromagnetic compatibility (EMC) of digital LSI chip mounted on a printed circuit board.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Buit-in noise monitor circuit / Multi-channel signal monitor / Signal integrity
Paper # CPM2007-134,ICD2007-145
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Committee ICD
Conference Date 2008/1/10(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On-Chip Monitoring Technique and Evaluation of Power-Supply Integrity
Sub Title (in English)
Keyword(1) Buit-in noise monitor circuit
Keyword(2) Multi-channel signal monitor
Keyword(3) Signal integrity
1st Author's Name Makoto NAGATA
1st Author's Affiliation Department of Computer Science and Systems Engineering, Graduate School of Engineering, Kobe University()
Date 2008-01-17
Paper # CPM2007-134,ICD2007-145
Volume (vol) vol.107
Number (no) 426
Page pp.pp.-
#Pages 6
Date of Issue