Presentation 2008-01-31
Analysis on 4RTD Logic Circuits
Tomohiko EBATA, Hiroki OKUYAMA, Takao WAHO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) 4RTD logic operation has been analyzed based on a circuit model, circuit simulation, and experiment. First, equations describing the biasing clock current that is required to obtain OR/AND and NOR/NAND logic operation are derived. Then, design principle to increase the operation margin in terms of the clock current is presented. Increasing the input current is most effective for that purpose. It is also found that the OR/AND circuit has a wider margin than the NOR/NAND circuit. These predictions have been proved by the circuit measurement.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) resonant-tunneling diode / RTD / logic circuit / circuit simulation / experiment
Paper # ED2007-248,SDM2007-259
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Conference Information
Committee SDM
Conference Date 2008/1/23(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis on 4RTD Logic Circuits
Sub Title (in English)
Keyword(1) resonant-tunneling diode
Keyword(2) RTD
Keyword(3) logic circuit
Keyword(4) circuit simulation
Keyword(5) experiment
1st Author's Name Tomohiko EBATA
1st Author's Affiliation Faculty of Science and Technology, Sophia University()
2nd Author's Name Hiroki OKUYAMA
2nd Author's Affiliation Faculty of Science and Technology, Sophia University
3rd Author's Name Takao WAHO
3rd Author's Affiliation Faculty of Science and Technology, Sophia University
Date 2008-01-31
Paper # ED2007-248,SDM2007-259
Volume (vol) vol.107
Number (no) 474
Page pp.pp.-
#Pages 6
Date of Issue