Presentation 2008-01-30
InP Ballistic Transistors
Yasuyuki MIYAMOTO, Kazuhito FURUYA,
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Abstract(in English) To minimize scattering of electron in electron devices, we proposed InP ballistics transistors. By Monte Carlo simulation, average speed of carrier is over 8×10^7cm/s. This speed is two times higher than the speed of reported conventional devices. When 2MA/cm^2 is assumed as current density, estimated cutoff frequency was over 1.4THz. Fabricated transistor with Schottky gate with 25nm-wide emitter by electron beam lithography showed voltage gain and current gain simultaneously, similar to conventional transistor structure. To reduce gate leakage current, transistors with insulated gates were also fabricated and current modulation by insulated gate was confirmed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) InP/InGaAs / ballistic electron / hot electron transistors / Monte Carlo simulation / insulated gate / electron beam lithography
Paper # ED2007-241,SDM2007-252
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Committee SDM
Conference Date 2008/1/23(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) InP Ballistic Transistors
Sub Title (in English)
Keyword(1) InP/InGaAs
Keyword(2) ballistic electron
Keyword(3) hot electron transistors
Keyword(4) Monte Carlo simulation
Keyword(5) insulated gate
Keyword(6) electron beam lithography
1st Author's Name Yasuyuki MIYAMOTO
1st Author's Affiliation Department of Physical Electronics, Tokyo Institute of Technology:CREST, Japan Science and Technology Corporation()
2nd Author's Name Kazuhito FURUYA
2nd Author's Affiliation Department of Physical Electronics, Tokyo Institute of Technology:CREST, Japan Science and Technology Corporation
Date 2008-01-30
Paper # ED2007-241,SDM2007-252
Volume (vol) vol.107
Number (no) 474
Page pp.pp.-
#Pages 6
Date of Issue