| Presentation | 2008-01-25 Design and Implement of SFQ Half-Precision Floating-Point Multiplier Hiroshi HARA, Kouji OBATA, Heejoung PARK, Yuki YAMANASHI, Kazuhiro TAKETOMI, Nobuyuki YOSHIKAWA, Masamitsu TANAKA, Yuki Ito, Akira FUJIMAKI, Naofumi TAKAGI, Kazuyoshi TAKAGI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum circuits as a fundamental technology for future high-end computing systems, which overcomes the power-consumption and memory-wall problems in the CMOS microprocessors. An SFQ LSRDP system is composed of several thousands of SFQ floating-point units that are connected by reconfigurable SFQ switch networks to achieve high-performance calculations with low power consumption. In this study, we have designed and implemented SFQ floating-point multipliers, which are one of the components of the SFQ LSRDP. We have designed a systolic-array-type bit-serial half-precision floating-point multiplier using 2.5kA/cm^2 Nb process. Resultant circuit area and the number of junctions are 6.22 x 3.78mm^2 and 11044, respectively. The designed clock frequency is 25GHz. We have also tested a 4-bit systolic-array multiplier, which is a circuit component of the floating-point-multiplier, and confirmed its correct operation at low speed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Superconducting integrated circuits / SFQ circuits / LSRDP / Multiplier / Floating point units |
| Paper # | SCE2007-32 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2008/1/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implement of SFQ Half-Precision Floating-Point Multiplier |
| Sub Title (in English) | |
| Keyword(1) | Superconducting integrated circuits |
| Keyword(2) | SFQ circuits |
| Keyword(3) | LSRDP |
| Keyword(4) | Multiplier |
| Keyword(5) | Floating point units |
| 1st Author's Name | Hiroshi HARA |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Kouji OBATA |
| 2nd Author's Affiliation | Department of Information Engineering, Nagoya University |
| 3rd Author's Name | Heejoung PARK |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Yuki YAMANASHI |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 5th Author's Name | Kazuhiro TAKETOMI |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 6th Author's Name | Nobuyuki YOSHIKAWA |
| 6th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 7th Author's Name | Masamitsu TANAKA |
| 7th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 8th Author's Name | Yuki Ito |
| 8th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 9th Author's Name | Akira FUJIMAKI |
| 9th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 10th Author's Name | Naofumi TAKAGI |
| 10th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 11th Author's Name | Kazuyoshi TAKAGI |
| 11th Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2008-01-25 |
| Paper # | SCE2007-32 |
| Volume (vol) | vol.107 |
| Number (no) | 458 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |