| Presentation | 2008-01-25 Design and Implementation of the SFQ Half-Precision Floating Point Adder Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which will be a fundamental technology for future petaflops-scale computing systems. The LSRDP is composed of a large number of floating-point units (FPUs) each of which is connected by reconfigurable routing networks. In the LSRDP, reputation loops in the source program are directly mapped to the LSRDP. The main advantage of the LSRDP is the reduction of the memory wall problem in the high-performance computing system. A memory access rate is considerably reduced, because the data are directly transferred between FPUs in the LSRDP without memory accesses. We have studied the architecture of an SFQ floating-point adder, which is a main circuit block in the SFQ LSRDP. We have designed an SFQ floating-point adder using the SRL 2.5kA/cm^2 niobium standard process. In this study, we will show the details of the design of the SFQ floating-point adder. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ logic circuit / Floating-point adder / large-scale reconfigurable data-path / shifter / normalizer |
| Paper # | SCE2007-31 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2008/1/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of the SFQ Half-Precision Floating Point Adder |
| Sub Title (in English) | |
| Keyword(1) | SFQ logic circuit |
| Keyword(2) | Floating-point adder |
| Keyword(3) | large-scale reconfigurable data-path |
| Keyword(4) | shifter |
| Keyword(5) | normalizer |
| 1st Author's Name | Heejoung Park |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Yuki Yamanashi |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Kazuhiro Taketomi |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Nobuyuki Yoshikawa |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 5th Author's Name | Masamitsu Tanaka |
| 5th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 6th Author's Name | Koji Obata |
| 6th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 7th Author's Name | Yuki Itou |
| 7th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 8th Author's Name | Akira Fujimaki |
| 8th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 9th Author's Name | Naofumi Takagi |
| 9th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 10th Author's Name | Kazuyoshi Takagi |
| 10th Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2008-01-25 |
| Paper # | SCE2007-31 |
| Volume (vol) | vol.107 |
| Number (no) | 458 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |