Presentation 2008-01-25
A CORDIC-based Reconfigurable Systolic Array Processor for MIMO-OFDM Wireless Communications
Katsutoshi Seki, Tomoyoshi Kobori, James Okello, Masao Ikekawa,
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Abstract(in English) A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the performance with other conventional processors, including EVP and ADRES. The processor achieves a computational density of 213% that of EVP. And, the processor achieves a active processing element rate of 213% that of ADRES.
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Keyword(in English) MIMO / OFDM / CORDIC / Systolic Array / Reconfigurable Processor
Paper # SR2007-72
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Committee SR
Conference Date 2008/1/17(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A CORDIC-based Reconfigurable Systolic Array Processor for MIMO-OFDM Wireless Communications
Sub Title (in English)
Keyword(1) MIMO
Keyword(2) OFDM
Keyword(3) CORDIC
Keyword(4) Systolic Array
Keyword(5) Reconfigurable Processor
1st Author's Name Katsutoshi Seki
1st Author's Affiliation NEC Corp.()
2nd Author's Name Tomoyoshi Kobori
2nd Author's Affiliation NEC Corp.
3rd Author's Name James Okello
3rd Author's Affiliation NEC Corp.
4th Author's Name Masao Ikekawa
4th Author's Affiliation NEC Corp.
Date 2008-01-25
Paper # SR2007-72
Volume (vol) vol.107
Number (no) 452
Page pp.pp.-
#Pages 6
Date of Issue