Presentation | 2007-12-19 How to design tables for power-analyses resistance of Table-network-based FPGA implementations of AES Makoto TORIKOSHI, Yoshio TAKAHASHI, Tsutomu MATSUMOTO, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Differential power analyses are statistical cryptanalytic methods to estimate the value of hidden cryptographic keys inside the module by utilizing the set of observed power consumption of the module, and they are threats that need countermeasures. As a countermeasure against differential power analyses we propose to apply the table-network-based implementations of block ciphers, which are originally designed for software tamper resistance against dynamic software analyses. Moreover, we describe how to design table for power analyses resistance of table-network-based hardware implementations. Based on experiments on table-network-based FPGA implementation of the Advanced Encryption Standard we describe and value the effectiveness of our proposal. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Cryptosystem / Side Channel Attack / Differential Power Analysis / Table / Key / FPGA / AES |
Paper # | ISEC2007-114 |
Date of Issue |
Conference Information | |
Committee | ISEC |
---|---|
Conference Date | 2007/12/12(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Information Security (ISEC) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | How to design tables for power-analyses resistance of Table-network-based FPGA implementations of AES |
Sub Title (in English) | |
Keyword(1) | Cryptosystem |
Keyword(2) | Side Channel Attack |
Keyword(3) | Differential Power Analysis |
Keyword(4) | Table |
Keyword(5) | Key |
Keyword(6) | FPGA |
Keyword(7) | AES |
1st Author's Name | Makoto TORIKOSHI |
1st Author's Affiliation | Graduate School of Environment and Information Sciences, Yokohama National University() |
2nd Author's Name | Yoshio TAKAHASHI |
2nd Author's Affiliation | Graduate School of Environment and Information Sciences, Yokohama National University:R & D Headquarters, NTT Data Corporation |
3rd Author's Name | Tsutomu MATSUMOTO |
3rd Author's Affiliation | Graduate School of Environment and Information Sciences, Yokohama National University |
Date | 2007-12-19 |
Paper # | ISEC2007-114 |
Volume (vol) | vol.107 |
Number (no) | 397 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |