Presentation 2007-12-19
Verification of DPA against XOR in hardware implementation of AES
Yohei TSUJI, Keisuke IWAI, Takakazu KUROKAWA,
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Abstract(in English) DPA techniques against cryptographic devices based on hardware implementation utilize the transition probability of bit signals. Authors propose a DPA technique using the difference of power consumption between rising transition (0→1) and falling the transition (1→0) of an output signal in CMOS devices. The result of DPA verification against the XOR operation in Add RoundKey, a part of AES circuit on FPGA, show to be able to specify a part of the private key.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Side Channel Attack / DPA / XOR / AES / FPGA
Paper # ISEC2007-113
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Conference Information
Committee ISEC
Conference Date 2007/12/12(1days)
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Paper Information
Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Verification of DPA against XOR in hardware implementation of AES
Sub Title (in English)
Keyword(1) Side Channel Attack
Keyword(2) DPA
Keyword(3) XOR
Keyword(4) AES
Keyword(5) FPGA
1st Author's Name Yohei TSUJI
1st Author's Affiliation Department of Computer Science, National Defense Academy()
2nd Author's Name Keisuke IWAI
2nd Author's Affiliation Department of Computer Science, National Defense Academy
3rd Author's Name Takakazu KUROKAWA
3rd Author's Affiliation Department of Computer Science, National Defense Academy
Date 2007-12-19
Paper # ISEC2007-113
Volume (vol) vol.107
Number (no) 397
Page pp.pp.-
#Pages 6
Date of Issue