Presentation 2007-12-19
A Scheduling of Shuffled BP Decoding Considering Pipelining Delay
Kazuya YOKOHARI, Yoshihiro SUGAYA, Hirotomo ASO,
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Abstract(in English) Shuffled BP decoding is known as a decoding method which has good decoding performance for low-density parity-check (LDPC) code. When Shuffled BP decoding is pipelined, some delays are required by processing time at a row process and a column process. In this paper, we propose a scheduling of Shuffled BP decoding considering pipelining delay and a construction method of parity check matrix which does not lead to a latency. Simulation results show that decoding performance of LDPC code constructed by the proposed method of parity check matrix has similar property of bit error ratio of LDPC code constructed by Array Code.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low-Density Parity-Check (LDPC) Code / Sum-Product Decoding / Shuffled BP Decoding / Array LDPC Code
Paper # CPSY2007-44
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Committee CPSY
Conference Date 2007/12/12(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Scheduling of Shuffled BP Decoding Considering Pipelining Delay
Sub Title (in English)
Keyword(1) Low-Density Parity-Check (LDPC) Code
Keyword(2) Sum-Product Decoding
Keyword(3) Shuffled BP Decoding
Keyword(4) Array LDPC Code
1st Author's Name Kazuya YOKOHARI
1st Author's Affiliation Graduate School of Engineering, Tohoku University()
2nd Author's Name Yoshihiro SUGAYA
2nd Author's Affiliation Graduate School of Engineering, Tohoku University
3rd Author's Name Hirotomo ASO
3rd Author's Affiliation Graduate School of Engineering, Tohoku University
Date 2007-12-19
Paper # CPSY2007-44
Volume (vol) vol.107
Number (no) 398
Page pp.pp.-
#Pages 6
Date of Issue