| Presentation | 2007-11-22 Proposal for Optimal LDPC Code Design System Yukari ISHIDA, Hirotaka NOSATO, Yosuke IIJIMA, Eiichi TAKAHASHI, Tatsumi FURUYA, Tetsuya HIGUCHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, LDPC (Low Density Parity Check) codes are attracting attention due to the considerable potential for error correction. Generally, an LDPC code is defined by a binary matrix known as a "check matrix". However, the lack of systematic methods of constructing check matrices represents a serious bottleneck to real-world applications. The paper proposes an optimal LDPC code design system that employs stochastic search algorithms and field programmable gate arrays (FPGA). The proposed system is able to identify LDPC codes at high-performance level for error correction and implement them at high-speeds and with a small number of logic elements. Specifically, the system stochastically searches for the optimal codes through a multi-objective optimization technique that enhances selection from among numerous candidates that have trade-off relationships. Moreover, a communication system emulator using FPGAs evaluates each code and determines its performance. This paper describes the proposed system, its structure, and presents the results of an experiment conducted to evaluate its effectiveness. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Error Correcting Code / LDPC / Reconfigurable Hardware / FPGA / multipurpose optimization technique / GA |
| Paper # | RECONF2007-47 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/11/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal for Optimal LDPC Code Design System |
| Sub Title (in English) | |
| Keyword(1) | Error Correcting Code |
| Keyword(2) | LDPC |
| Keyword(3) | Reconfigurable Hardware |
| Keyword(4) | FPGA |
| Keyword(5) | multipurpose optimization technique |
| Keyword(6) | GA |
| 1st Author's Name | Yukari ISHIDA |
| 1st Author's Affiliation | Toho University() |
| 2nd Author's Name | Hirotaka NOSATO |
| 2nd Author's Affiliation | Toho University |
| 3rd Author's Name | Yosuke IIJIMA |
| 3rd Author's Affiliation | University of Tsukuba |
| 4th Author's Name | Eiichi TAKAHASHI |
| 4th Author's Affiliation | National Institute of Advanced Industrial Science and Technology |
| 5th Author's Name | Tatsumi FURUYA |
| 5th Author's Affiliation | Toho University |
| 6th Author's Name | Tetsuya HIGUCHI |
| 6th Author's Affiliation | National Institute of Advanced Industrial Science and Technology |
| Date | 2007-11-22 |
| Paper # | RECONF2007-47 |
| Volume (vol) | vol.107 |
| Number (no) | 342 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |