Presentation 2007-11-22
A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism
Yuta IMAI, Kazunori SHIMIZU, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recently, needs for downloading digital contents via wireless network have been dramatically increasing as high-functionalization of portable music player and mobile phone had proceeded and the digitalization of broadcasting had been done. For that reason it is now essential to support high communication quality in a situation where communication environment is unstable. Low Density Parity Check(LDPC) code is expected to be an error correcting code for next generation since it shows high error correcting performance. Many experiments have been carried out on this topic. At present LDPC code is incorporated in IEEE802.11n which is next standard of wireless network. In this paper, we propose area-saving LDPC decoder which can show a high decoding performance under unstalbe wireless communication environment. This is done by sharing adders within the column operational module among different information rates. Our method can also increase a parallelism of operation as an information rate gets higher so that the decoder shows higher decoding throughtput compared to the conventional decoders.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) LDPC Decoder / Irregular / Multi-Rate / column operation
Paper # RECONF2007-46
Date of Issue

Conference Information
Committee RECONF
Conference Date 2007/11/15(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism
Sub Title (in English)
Keyword(1) LDPC Decoder
Keyword(2) Irregular
Keyword(3) Multi-Rate
Keyword(4) column operation
1st Author's Name Yuta IMAI
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Kazunori SHIMIZU
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Nozomu TOGAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Masao YANAGISAWA
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
5th Author's Name Tatsuo OHTSUKI
5th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2007-11-22
Paper # RECONF2007-46
Volume (vol) vol.107
Number (no) 342
Page pp.pp.-
#Pages 6
Date of Issue