| Presentation | 2007-11-22 Performance evaluation of reconfigurable architecture based on digit-serial computation Takuro UCHIDA, Tetsuya ZUYAMA, Kazuya TANIGAWA, Tetsuo HIRONAKA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a core architecture which has RISC processor and DS-HIE reconfigurable architecture. This architecture is called as Hybrid DS Core (Hy-DiSC) architecture. This paper evaluates the effect of DS-HIE architecture in the point of performance and transistor counts. The test program for evaluation is JPEG encoding. On the test program DS-HIE architecture accelerates DCT processing for JPEG encoding. In a execution of DCT, Hy-DiSC architecture achieves 4.32 times higher performances, compared with the execution time of RISC processor without accelerating by DS-HIE processor. And all over performance of Hy-DiSC architecture executed JPEG encoding, it achieves 1.55 times higher performance. While on JPEG encoding the transistor counts of DS-HIE architecture is 1/11 times in comparison with one core in Core2 Duo processor. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamic Reconfigurable Architecture / Digit-serial / Benes Network |
| Paper # | RECONF2007-44 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/11/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance evaluation of reconfigurable architecture based on digit-serial computation |
| Sub Title (in English) | |
| Keyword(1) | Dynamic Reconfigurable Architecture |
| Keyword(2) | Digit-serial |
| Keyword(3) | Benes Network |
| 1st Author's Name | Takuro UCHIDA |
| 1st Author's Affiliation | Graduate school of information Sciences, Hiroshima City University() |
| 2nd Author's Name | Tetsuya ZUYAMA |
| 2nd Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Graduate school of information Sciences, Hiroshima City University |
| Date | 2007-11-22 |
| Paper # | RECONF2007-44 |
| Volume (vol) | vol.107 |
| Number (no) | 342 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |