Presentation 2007-11-22
Designing Soft Error Tolerant LUTs of SRAM-based FPGAs
Kohei SATOYAMA, Takashi NAKADA, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA,
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Abstract(in English) Recently, soft error becomes a serious problem as the process shrinks. Especially, SRAMs seriously suffer from soft error, and thus various techniques have been proposed to deal with it. In this paper, we proposes a technique, which we call "XOR swap," to achieve the majority voting of the TMR (Triple Module Redundancy) by using only the double memory cost. This technique can correct arbitrary random 1-bit error, and we confirmed that the error tolerance by the proposed technique is almost the same as that of TMR.
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Keyword(in English) Soft error / FPGA / LUT / TMR
Paper # RECONF2007-43
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Committee RECONF
Conference Date 2007/11/15(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Designing Soft Error Tolerant LUTs of SRAM-based FPGAs
Sub Title (in English)
Keyword(1) Soft error
Keyword(2) FPGA
Keyword(3) LUT
Keyword(4) TMR
1st Author's Name Kohei SATOYAMA
1st Author's Affiliation Nara Institute of Science and Technology()
2nd Author's Name Takashi NAKADA
2nd Author's Affiliation Nara Institute of Science and Technology
3rd Author's Name Masaki NAKANISHI
3rd Author's Affiliation Nara Institute of Science and Technology
4th Author's Name Shigeru YAMASHITA
4th Author's Affiliation Nara Institute of Science and Technology
5th Author's Name Yasuhiko NAKASHIMA
5th Author's Affiliation Nara Institute of Science and Technology
Date 2007-11-22
Paper # RECONF2007-43
Volume (vol) vol.107
Number (no) 342
Page pp.pp.-
#Pages 6
Date of Issue