Presentation | 2007-11-21 A low power consumption processor with on-chip control mechanism using pipeline stage unification Katsuya KIMURA, Ryotaro KOBAYASHI, Toshio SHIMADA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we implement and estimate the low power consumption processor which uses Pipeline Stage Unification (PSU) with on-chip control mechanism in FPGA. We employed an embedded processor with 32-bit width 6 stages pipeline. The on-chip control mechanism dynamically changes number of pipeline stages (6 stages, 3 stages and 2 stages). The evaluation results show that the mechanism can reduce average power consumption by 6.3% and energy consumption by 9.8% compared with Dynamic Voltage and Frequency Scaling. Area increase by PSU implementation is 15.3%. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | low-power / Pipeline Stage Unification(PSU) / throughput controller |
Paper # | RECONF2007-42 |
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Committee | RECONF |
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Conference Date | 2007/11/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A low power consumption processor with on-chip control mechanism using pipeline stage unification |
Sub Title (in English) | |
Keyword(1) | low-power |
Keyword(2) | Pipeline Stage Unification(PSU) |
Keyword(3) | throughput controller |
1st Author's Name | Katsuya KIMURA |
1st Author's Affiliation | Graduate School of Engineering, Nagoya University() |
2nd Author's Name | Ryotaro KOBAYASHI |
2nd Author's Affiliation | Graduate School of Engineering, Nagoya University |
3rd Author's Name | Toshio SHIMADA |
3rd Author's Affiliation | Graduate School of Engineering, Nagoya University |
Date | 2007-11-21 |
Paper # | RECONF2007-42 |
Volume (vol) | vol.107 |
Number (no) | 341 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |