Presentation 2007-11-20
Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield
Yuuri SUGIHARA, Youhei KUME, Kazutoshi KOBAYASHI, Hidetoshi ONODERA,
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Abstract(in English) FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variations. We propose variation-aware reconfiguration which utilizes these variations for performance enhancement. We have fabricated and measured 90nm FPGAs, in which random variations without spatial correlations are dominant. To utilize these random variations for performance enhancement, optimizing each device from a common configuration is better than producing optimized configurations according to detailed measurement results. In this paper we apply the track swapping procedure to critical path reconfiguration which obtains an optimized configuration to repeat measurement and reconfiguration. First we configure all fabricated FPGAs with a common configuration data. The configuration of each die is optimized to reroute the critical paths that does not meet timing specifications. Rerouting of a critical path usually causes drastic topology changes which may prolong other paths and will create new critical paths. In the track swapping procedure, we swap a wire track on a critical path for the adjacent track without any topology change. It can be realized to use switch blocks with more flexibility. We experiment performance enhancement by applying the track swapping to LGSynth93 benchmark circuits. We achieve 5.81% of speed enhancement and 26.62% of yield enhancement.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Variation / FPGA / Reconfigure / Yield
Paper # RECONF2007-34
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Conference Information
Committee RECONF
Conference Date 2007/11/13(1days)
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Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield
Sub Title (in English)
Keyword(1) Variation
Keyword(2) FPGA
Keyword(3) Reconfigure
Keyword(4) Yield
1st Author's Name Yuuri SUGIHARA
1st Author's Affiliation Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University()
2nd Author's Name Youhei KUME
2nd Author's Affiliation Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University
3rd Author's Name Kazutoshi KOBAYASHI
3rd Author's Affiliation Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University
4th Author's Name Hidetoshi ONODERA
4th Author's Affiliation Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University
Date 2007-11-20
Paper # RECONF2007-34
Volume (vol) vol.107
Number (no) 340
Page pp.pp.-
#Pages 6
Date of Issue