| Presentation | 2007-11-20 A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori MATSUYAMA, Ryoichi YAMAGUCHI, Yoshiaki SATOU, Hiroshi MIURA, Masahiro KOGA, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can be varied according to various computations in an application. VGLC can be implemented all of 2,3,4-input logic functions. However, when we forcus on its architecture, not only under 4-input but over 5-input logic functions can be implemented in one VGLC. In order to consider this case, it is necessary to use boolean matching method with logic functions of a mapping circuit. This paper shows mapping method with VGLC, and evaluates area and delay. As a result, the area is decreased by 58.9%, and the delay is reduced by 25.9% in the benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic device / coarse-grain / fine-grain / multiple inputs logic / boolean matching |
| Paper # | RECONF2007-33 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/11/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic device |
| Keyword(2) | coarse-grain |
| Keyword(3) | fine-grain |
| Keyword(4) | multiple inputs logic |
| Keyword(5) | boolean matching |
| 1st Author's Name | Kazunori MATSUYAMA |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Ryoichi YAMAGUCHI |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Yoshiaki SATOU |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Hiroshi MIURA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Masahiro KOGA |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 6th Author's Name | Kazuki INOUE |
| 6th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 7th Author's Name | Motoki AMAGASAKI |
| 7th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 8th Author's Name | Masahiro IIDA |
| 8th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 9th Author's Name | Toshinori SUEYOSHI |
| 9th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2007-11-20 |
| Paper # | RECONF2007-33 |
| Volume (vol) | vol.107 |
| Number (no) | 340 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |