| Presentation | 2007-11-20 A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto, Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto, Masaya Yoshikawa, Tomonori Izumi, Takeshi Fujino, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a ePLX (embedded Programmable Logic matriX) which will be embedded in SoC. The ePLX consists of small area and a few wiring layer to enhance programmability maintaining performance on SoC. ePLX architecture consists of 2LUT-array cluster and wiring block which is composed of wire between local clusters. They are alternately placed. Local cluster is composed of two input Look-Up-Table (LUT) array, limited and high speed wiring switch between LUTs and the D-FlipFlops on the array side. In order to implement a target function on the ePLX, we need to develop a automatic mapping and routing tools. In this paper, we explain auto mapping and routing flowchart and report study of local cluster auto mapping tools. We also report study of other local architectures. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | programmable device / SoC / automatic mapping |
| Paper # | RECONF2007-32 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/11/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture |
| Sub Title (in English) | |
| Keyword(1) | programmable device |
| Keyword(2) | SoC |
| Keyword(3) | automatic mapping |
| 1st Author's Name | Kouta Ishibashi |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan Univesity() |
| 2nd Author's Name | Yoshiyuki Tanaka |
| 2nd Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Mitsutaka Matsumoto |
| 3rd Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan Univesity |
| 4th Author's Name | Hirofumi Nakano |
| 4th Author's Affiliation | Renesas Technology Corp. |
| 5th Author's Name | Takenobu Iwao |
| 5th Author's Affiliation | Renesas Technology Corp. |
| 6th Author's Name | Yoshihiro Okuno |
| 6th Author's Affiliation | Renesas Technology Corp. |
| 7th Author's Name | Kazutami Arimoto |
| 7th Author's Affiliation | Renesas Technology Corp. |
| 8th Author's Name | Masaya Yoshikawa |
| 8th Author's Affiliation | Graduate School of Science and Engineering, Meijo University |
| 9th Author's Name | Tomonori Izumi |
| 9th Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan Univesity |
| 10th Author's Name | Takeshi Fujino |
| 10th Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan Univesity |
| Date | 2007-11-20 |
| Paper # | RECONF2007-32 |
| Volume (vol) | vol.107 |
| Number (no) | 340 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |