| Presentation | 2007-11-21 A power masking multiplier based on galois field for composite field AES Nobuyuki KAWAHATA, Ryuta NARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | AES is one of common key cryptosystems and mainly used on an embedded system, IC-chip and others, and the common key must not known by others. However the common key can be cracked by side channel attack (SCA). SCA, an attacking method of cracking common key by measuring and analyzing physical quantity at the encryption processing, is proposed and pointed as a dangerous for the security of AES. Especialy in SCA, the attacking method that is the most dangerous and realistic for security of AES is to be a deffirential power analysis (DPA). Hence against DPA, SubBytes circuit is needed to design as an anti-DPA. To design an anti-DPA SubBytes circuit, we propose a power masking multiplier based on galois field for composite field AES. With the multiplier, we design a circuit of inverse-element based on galois field for composite field and design SubBytes circuit oriented low area by using it. We report evaluation and result. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Differential power analysis (DPA) / Composite field / AES / IC-chip / Embeded system |
| Paper # | VLD2007-88,DC2007-43 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/11/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A power masking multiplier based on galois field for composite field AES |
| Sub Title (in English) | |
| Keyword(1) | Differential power analysis (DPA) |
| Keyword(2) | Composite field |
| Keyword(3) | AES |
| Keyword(4) | IC-chip |
| Keyword(5) | Embeded system |
| 1st Author's Name | Nobuyuki KAWAHATA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Ryuta NARA |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2007-11-21 |
| Paper # | VLD2007-88,DC2007-43 |
| Volume (vol) | vol.107 |
| Number (no) | 338 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |