Presentation 2007-11-21
A Construction Method of Path Delay Fault Detectable Circuits
Takashi WATANABE, Takeo YOSHIDA,
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Abstract(in English) In this paper, we propose a construction method of path delay fault detectable circuits. A value of each register in synchronous sequential circuits is neccessary to be checked because of path delay faults affect it. In this paper, we detect path delay faults by observing whether a value of resister is a code word or a non-codeword, after both the input and the output of combinational circuits in sequential circuits are encoded to an error detecting code. To detect path delay faults, we show conditions which the error detecting code and construction of the circuit should satisfy. And we describe a method to construct path delay fault detectable circuits. By using our method, we can easily design path delay fault detectable circuits. We also show that the evaluation of ITC'99 benchmark circuits which are adopted our method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Path Delay Fault / Fault Detection / Wiring Delay / Equidistant Code
Paper # VLD2007-85,DC2007-40
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Committee DC
Conference Date 2007/11/14(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Construction Method of Path Delay Fault Detectable Circuits
Sub Title (in English)
Keyword(1) Path Delay Fault
Keyword(2) Fault Detection
Keyword(3) Wiring Delay
Keyword(4) Equidistant Code
1st Author's Name Takashi WATANABE
1st Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus()
2nd Author's Name Takeo YOSHIDA
2nd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
Date 2007-11-21
Paper # VLD2007-85,DC2007-40
Volume (vol) vol.107
Number (no) 338
Page pp.pp.-
#Pages 6
Date of Issue