| Presentation | 2007-11-21 Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning Thomas Edison YU, Tomokazu YONEDA, Krishnendu CHAKRABARTY, Hideo FUJIWARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Higher power densities and the non-linear spatial distribution of heat of VLSI chips put greater emphasis on chip-packaging and temperature control during test. For system-on-chips, power-based scheduling algorithms are used to optimize tests while satisfying power budgets. However, it has been shown that power-constrained test scheduling does not ensure thermal safety due to the non-uniform power distribution across the chip. In this paper, we present a test schedule optimization method for system-on-chips using cycle-accurate power profiles for thermal simulation, test partitioning, and interleaving that ensures thermal safety while still optimizing the test schedule. Our method uses a simplified thermal-cost model and bin-packing algorithm to ensure that the maximum temperatures of SoCs with fixed TAM and core assignments satisfy the temperature constraints with minimum increases in test application time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC test / thermal constraint / wrapper design / TAM design / test scheduling |
| Paper # | VLD2007-84,DC2007-39 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/11/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning |
| Sub Title (in English) | |
| Keyword(1) | SoC test |
| Keyword(2) | thermal constraint |
| Keyword(3) | wrapper design |
| Keyword(4) | TAM design |
| Keyword(5) | test scheduling |
| 1st Author's Name | Thomas Edison YU |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Krishnendu CHAKRABARTY |
| 3rd Author's Affiliation | Electrical and Computer Engineering, Duke University |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2007-11-21 |
| Paper # | VLD2007-84,DC2007-39 |
| Volume (vol) | vol.107 |
| Number (no) | 338 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |