| Presentation | 2007-11-20 Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yosiaki Shitabayshi, Takeshi Fujino, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can change the logic of a digital circuit by changing two via-layer. Our novel device does not use photo-mask to change digital-circuit logic, because we use Electron Beam (EB) direct writing which is mask-less lithography. Therefore, we can cut mask cost, completely. The logic element (LE) of VPEX is composed of complex gate type EXclusive-OR (EXOR) and Inverter(INV). The single LE can outputs 12 logic functions which include all2-input logic functions by changing via-1 layer. Moreover, D-FlipFlop (DFF) consists of 5 LEs. Therefore there is no dead space unlike FPGA. In the paper, we compare performance of VPEX logic functions with that of standard-cells (Std) in 0.18μm CMOS technology. In addition, small-scale circuits of VPEX and Std are evaluated by area, delay-time and power-consumption. Finally, we discuss about comparison performance of VPEX with that of other works of via-programmable devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Via-programmable logic / EB direct writing / Exclusive-OR / structured ASIC |
| Paper # | VLD2007-80,DC2007-35 |
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| Committee | DC |
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| Conference Date | 2007/11/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing |
| Sub Title (in English) | |
| Keyword(1) | Via-programmable logic |
| Keyword(2) | EB direct writing |
| Keyword(3) | Exclusive-OR |
| Keyword(4) | structured ASIC |
| 1st Author's Name | Masahide Kawarasaki |
| 1st Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Akihiro Nakamura |
| 2nd Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Tomoaki Nishimoto |
| 3rd Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Yosiaki Shitabayshi |
| 4th Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 5th Author's Name | Takeshi Fujino |
| 5th Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University:Faculty of Science and Engineering, Ritsumeikan University |
| Date | 2007-11-20 |
| Paper # | VLD2007-80,DC2007-35 |
| Volume (vol) | vol.107 |
| Number (no) | 337 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |