Presentation 2007-11-20
An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
Masaki YAMAGUCHI, Masanori MUROYAMA, Tohru ISHIHARA, Hiroto YASUURA,
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Abstract(in English) As the transistor size shrinks, the horizontal coupling capacitance between adjacent wires becomes dominant for wire load. Especially for an on-chip bus, since each line of a bus runs in parallel for a long distance, inter-wire coupling capacitance is larger than other interconnects. An interconnect delay increase caused by inter-wire coupling capacitance increase. Also, as the transistor size shrinks, process variations increase. With process variations, delay variations cause the yield loss. In this paper, we propose an on-chip bus architecture for post-fabrication timing calibration.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Process Variation / Deep Sub-Micron / Post-Fabrication Performance Compensation / CMOS
Paper # VLD2007-79,DC2007-34
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Committee DC
Conference Date 2007/11/13(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
Sub Title (in English)
Keyword(1) Process Variation
Keyword(2) Deep Sub-Micron
Keyword(3) Post-Fabrication Performance Compensation
Keyword(4) CMOS
1st Author's Name Masaki YAMAGUCHI
1st Author's Affiliation Graduate School of Information Science and Electrical Engineering, Kyushu University()
2nd Author's Name Masanori MUROYAMA
2nd Author's Affiliation System LSI Research Center, Kyushu University
3rd Author's Name Tohru ISHIHARA
3rd Author's Affiliation System LSI Research Center, Kyushu University
4th Author's Name Hiroto YASUURA
4th Author's Affiliation Graduate School of Information Science and Electrical Engineering, Kyushu University
Date 2007-11-20
Paper # VLD2007-79,DC2007-34
Volume (vol) vol.107
Number (no) 337
Page pp.pp.-
#Pages 6
Date of Issue