Presentation 2007-11-20
A process-variation-aware low-power technique using current control
Kyundong KIM, Masashi IMAI, Masaaki KONDO, Hiroshi NAKAMURA, Takashi NANYA,
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Abstract(in English) Due to process variations, the difference of the operation speed between pipeline stages is increased, resulting in a number of stages which have enough cycle-time because cycle-time depends heavily on that of the slowest stage. This paper propose a method which can reduce the dynamic power by activating the number of sleep transistors of the stages with both enough cycle-time and the power gating operation.
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Keyword(in English) Low power / Process variation / Power gating
Paper # VLD2007-76,DC2007-31
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Committee DC
Conference Date 2007/11/13(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A process-variation-aware low-power technique using current control
Sub Title (in English)
Keyword(1) Low power
Keyword(2) Process variation
Keyword(3) Power gating
1st Author's Name Kyundong KIM
1st Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo()
2nd Author's Name Masashi IMAI
2nd Author's Affiliation Komaba Open Laboratory, The University of Tokyo
3rd Author's Name Masaaki KONDO
3rd Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
4th Author's Name Hiroshi NAKAMURA
4th Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
5th Author's Name Takashi NANYA
5th Author's Affiliation Research Center for Advanced Science and Technology, The University of Tokyo
Date 2007-11-20
Paper # VLD2007-76,DC2007-31
Volume (vol) vol.107
Number (no) 337
Page pp.pp.-
#Pages 6
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