Presentation | 2007-11-20 An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko ISHITOBI, Tohru ISHIHARA, Hiroto YASUURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories and off-chip memories in embedded systems. We proposed a code placement method to minimize the total energy consumption considering a cacheable region, the scratchpad region and the non-cacheable region. The cacheable region uses cache memory at access, the scratchpad region uses SPM and the non-cacheable region accesses off-chip memory directly. The code placement problem to three region is formulated and proposeed the ILP model in this paper. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | energy reduction / embedded processor / code placement / scratchpad memory |
Paper # | VLD2007-75,DC2007-30 |
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Committee | DC |
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Conference Date | 2007/11/13(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors |
Sub Title (in English) | |
Keyword(1) | energy reduction |
Keyword(2) | embedded processor |
Keyword(3) | code placement |
Keyword(4) | scratchpad memory |
1st Author's Name | Yuriko ISHITOBI |
1st Author's Affiliation | Graduate School of Inf. Sci. & E.E., Kyushu University() |
2nd Author's Name | Tohru ISHIHARA |
2nd Author's Affiliation | System LSI Research Center, Kyushu University |
3rd Author's Name | Hiroto YASUURA |
3rd Author's Affiliation | Faculty of Inf. Sci. & E.E., Kyushu University |
Date | 2007-11-20 |
Paper # | VLD2007-75,DC2007-30 |
Volume (vol) | vol.107 |
Number (no) | 337 |
Page | pp.pp.- |
#Pages | 6 |
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