| Presentation | 2007-11-20 An Optimization of Thru Trees for Test Generation Based on Acyclical Testability Kohsuke MORINAGA, Nobuya OKA, Yuki YOSHIKAWA, Hideyuki ICHIHARA, Tomoo INOUE, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The class of acyclic sequential circuits is τ^2-bounded, i.e., acyclic sequential circuits are practically easily testable [2], [3]. Further, classes of acyclically testable sequential circuits [4] and extended acyclically testable ones [5], which are larger than that of acyclic sequential circuits, have been proposed. A key condition for acyclical/extended acyclical testability is defined mainly by means of thru functions, and hence, a given sequential circuit can be modified into such testable circuits by adding thru functions. Consequently, the DFT overhead can be reduced compared to conventional full scan design. This paper presents a method for implementing optimal thru trees which minimize the hardware cost required for extended acyclical testability of a given sequential circuits. We formulate the optimization problem on design for testability with thru trees based on extended acyclical testability, and express the formulation as an integer linear programming (ILP) model. Experimental results show the effectiveness of our formulation, and also demonstrate the effectiveness of the class of extended acyclical testability. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test generation / design-for-testability / acyclical testability / extended acyclical testability / integer linear programming (ILP) |
| Paper # | VLD2007-72,DC2007-27 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2007/11/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Optimization of Thru Trees for Test Generation Based on Acyclical Testability |
| Sub Title (in English) | |
| Keyword(1) | test generation |
| Keyword(2) | design-for-testability |
| Keyword(3) | acyclical testability |
| Keyword(4) | extended acyclical testability |
| Keyword(5) | integer linear programming (ILP) |
| 1st Author's Name | Kohsuke MORINAGA |
| 1st Author's Affiliation | Guraduate of Infomation Sciences, Hiroshima City University() |
| 2nd Author's Name | Nobuya OKA |
| 2nd Author's Affiliation | Guraduate of Infomation Sciences, Hiroshima City University |
| 3rd Author's Name | Yuki YOSHIKAWA |
| 3rd Author's Affiliation | Guraduate of Infomation Sciences, Hiroshima City University |
| 4th Author's Name | Hideyuki ICHIHARA |
| 4th Author's Affiliation | Guraduate of Infomation Sciences, Hiroshima City University |
| 5th Author's Name | Tomoo INOUE |
| 5th Author's Affiliation | Guraduate of Infomation Sciences, Hiroshima City University |
| Date | 2007-11-20 |
| Paper # | VLD2007-72,DC2007-27 |
| Volume (vol) | vol.107 |
| Number (no) | 334 |
| Page | pp.pp.- |
| #Pages | 6 |
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