Presentation	2007-11-18 Four Valued SRAM with Neuron MOSFETs Yoshiaki HIRATA, Yoshikazu ISHIMARU, Akio SHIMIZU, Sumio FUKAI,
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Abstract(in English)	In this paper, we propose Four Valued SRAM that use a changeable threshold of neuron MOS transistor (νMOSFETs) as a mean to identify multivalued signals. νMOSFETs not only bringing production costs down with standard CMOS process, but also facilitating coexistence with binary logical circuit. Four Valued SRAM is circuit that can preserve signals in two bits per one memory cell by using four signals of 0, 1, 2, and 3. We compare the proposal circuit with the conventional circuit regarding the area of the circuit, operation speed, and power consumption of the SRAM cell. The proposed circuit is designed by using device parameter of standard CMOS 1.2μm process. The performance of Four Valued SRAM cell is evaluated by HSPICE simulation.
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Keyword(in English)	neuron MOSFETs / Four Valued SRAM
Paper #	NC2007-62
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Committee	NC
Conference Date	2007/11/11(1days)
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Paper Information
Registration To	Neurocomputing (NC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Four Valued SRAM with Neuron MOSFETs
Sub Title (in English)
Keyword(1)	neuron MOSFETs
Keyword(2)	Four Valued SRAM
1st Author's Name	Yoshiaki HIRATA
1st Author's Affiliation	Saga University()
2nd Author's Name	Yoshikazu ISHIMARU
2nd Author's Affiliation	Saga University
3rd Author's Name	Akio SHIMIZU
3rd Author's Affiliation	Saga University
4th Author's Name	Sumio FUKAI
4th Author's Affiliation	Saga University
Date	2007-11-18
Paper #	NC2007-62
Volume (vol)	vol.107
Number (no)	328
Page	pp.pp.-
#Pages	6
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