Presentation 2007-11-18
Evaluation of a CMOS Spiking Neural Network LSI with STDP Function
Hideki TANAKA, Takashi MORIE, Kazuyuki AIHARA,
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Abstract(in English) In some spiking neuron models, analog information is expressed by the timing of neuronal spike firing events, and synaptic weights change depending on the relative timing between asynchronous spikes, which is called spike-timing dependent synaptic plasticity (STDP). In this paper, we report the measurement results of a CMOS spiking neuron circuit with STDP function and a spiking feedback network circuit.
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Keyword(in English) spiking neuron / neural network / STDP(Spike-Timing Dependent synaptic Plasticity) / analog CMOS circuit
Paper # NC2007-61
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Committee NC
Conference Date 2007/11/11(1days)
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Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of a CMOS Spiking Neural Network LSI with STDP Function
Sub Title (in English)
Keyword(1) spiking neuron
Keyword(2) neural network
Keyword(3) STDP(Spike-Timing Dependent synaptic Plasticity)
Keyword(4) analog CMOS circuit
1st Author's Name Hideki TANAKA
1st Author's Affiliation Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology()
2nd Author's Name Takashi MORIE
2nd Author's Affiliation Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology
3rd Author's Name Kazuyuki AIHARA
3rd Author's Affiliation Institute of Industrial Science, The University of Tokyo, and Aihara Complexity Modelling Project, ERATO, JST
Date 2007-11-18
Paper # NC2007-61
Volume (vol) vol.107
Number (no) 328
Page pp.pp.-
#Pages 6
Date of Issue