Presentation | 2007-10-18 Derivation of Circuit Level Specifications of ΔΣ Modulator Based on Behavioral Modeling and Simulation Yasuji IKEDA, Hideki ASAI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A technique is presented for high-level synthesis using behavioral modeling of delta-sigma modulator. Verilog-A is used as the analog HDL (hardware description language) for behavioral modeling which enables to consider a variety of nonidealities. The block specification parameters which cause nonideal influence are expressed as the function of capacitor size and bias current. The method of optimizing those parameters and estimating current consumption by behavioral model simulation is described. By this method, SNR and current consumption for several topologies are estimated and the optimal parameters and the topology to target SNR are derived as a transistor level design specification. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Delta-sigma Modulator / Analog HDL / Behavioral modeling and simulation / Optimization |
Paper # | CAS2007-47,NLP2007-75 |
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Committee | NLP |
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Conference Date | 2007/10/11(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Nonlinear Problems (NLP) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Derivation of Circuit Level Specifications of ΔΣ Modulator Based on Behavioral Modeling and Simulation |
Sub Title (in English) | |
Keyword(1) | Delta-sigma Modulator |
Keyword(2) | Analog HDL |
Keyword(3) | Behavioral modeling and simulation |
Keyword(4) | Optimization |
1st Author's Name | Yasuji IKEDA |
1st Author's Affiliation | Graduate School of Engineering, Shizuoka University() |
2nd Author's Name | Hideki ASAI |
2nd Author's Affiliation | Graduate School of Engineering, Shizuoka University |
Date | 2007-10-18 |
Paper # | CAS2007-47,NLP2007-75 |
Volume (vol) | vol.107 |
Number (no) | 266 |
Page | pp.pp.- |
#Pages | 5 |
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