Presentation 2007-10-26
Performance Evaluation of Variable Length Encoder/Decoder Hardware for Multi-Codec
Takafumi YUASA, Hiroaki NAKATA, Kazushi AKIE, Fumitaka IZUHARA, Kenichi IWATA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We developed Variable Length Encoder/Decoder hardware for multi-codecs. Our hardware processes VLC(Variable Length Code)s using RAM Table to prevent the increase circuit size. The proposed architecture achieves performance of 1bit/3cycles for arbitrary VLC sequences and performance of 40Mbps bit-stream at 162MHz.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Codec / Variable Length Code / MPEG-2 / H.264
Paper # SIP2007-123,ICD2007-112,IE2007-82
Date of Issue

Conference Information
Committee IE
Conference Date 2007/10/19(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Image Engineering (IE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Evaluation of Variable Length Encoder/Decoder Hardware for Multi-Codec
Sub Title (in English)
Keyword(1) Codec
Keyword(2) Variable Length Code
Keyword(3) MPEG-2
Keyword(4) H.264
1st Author's Name Takafumi YUASA
1st Author's Affiliation Hitachi, Ltd., Central Research Laboratory()
2nd Author's Name Hiroaki NAKATA
2nd Author's Affiliation Hitachi, Ltd., Central Research Laboratory
3rd Author's Name Kazushi AKIE
3rd Author's Affiliation Renesas Technology Corp., System Solution Business Group
4th Author's Name Fumitaka IZUHARA
4th Author's Affiliation Renesas Technology Corp., System Solution Business Group
5th Author's Name Kenichi IWATA
5th Author's Affiliation Renesas Technology Corp., System Solution Business Group
Date 2007-10-26
Paper # SIP2007-123,ICD2007-112,IE2007-82
Volume (vol) vol.107
Number (no) 290
Page pp.pp.-
#Pages 5
Date of Issue