Presentation 2007-10-12
Analysis of Buffer-Related Slow Current Transients and Current Collapse in AlGaN/GaN HEMTs
Atsushi NAKAJIMA, Kazushige HORIO,
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Abstract(in English) Two-dimensional transient analyses of AlGaN/GaN HEMTs are performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. When the drain voltage is raised abruptly, electrons are injected into the buffer layer and captured by deep donors, and when it is lowered abruptly, the drain currents remain at low values for some periods and begin to increase slowly as the deep donors begin to emit electrons, showing drain-lag behavior. The gate lag could also occur due to deep levels in the buffer layer, and it is correlated with relatively high source access resistance in AlGaN/GaN HEMTs. It is shown that the current slump is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. The drain lag could be a major cause of current slump in the case of higher off-state drain voltage. It is suggested that to minimize current slump in AlGaN/GaN HEMTs, an acceptor density in the buffer layer should be made low, although there may be a trade-off relationship between reducing current slump and obtaining sharp current cutoff.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) GaN / HEMT / trap / current collapse / drain lag / gate lag / access resistance / device simulation
Paper # ED2007-169,CPM2007-95,LQE2007-70
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Conference Information
Committee LQE
Conference Date 2007/10/4(1days)
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Registration To Lasers and Quantum Electronics (LQE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis of Buffer-Related Slow Current Transients and Current Collapse in AlGaN/GaN HEMTs
Sub Title (in English)
Keyword(1) GaN
Keyword(2) HEMT
Keyword(3) trap
Keyword(4) current collapse
Keyword(5) drain lag
Keyword(6) gate lag
Keyword(7) access resistance
Keyword(8) device simulation
1st Author's Name Atsushi NAKAJIMA
1st Author's Affiliation Faculty of Systems Engineering, Shibaura Institute of Technology()
2nd Author's Name Kazushige HORIO
2nd Author's Affiliation Faculty of Systems Engineering, Shibaura Institute of Technology
Date 2007-10-12
Paper # ED2007-169,CPM2007-95,LQE2007-70
Volume (vol) vol.107
Number (no) 253
Page pp.pp.-
#Pages 6
Date of Issue