Presentation 2007-10-25
Study on a TOPS scale architecture
Hiroshi SUZUKI, Takao NISHITANI, Bin Wu, Hachiro FUJITA,
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Abstract(in English) This paper describes a novel architecture of digital signal processor (DSP) for future portable equipment. This architecture has many cores, and operates in parallel for low power dissipation and for improvement of operation performance. Interconnect among neighboring processors can be switched to either path or bus for efficient data transition. As many recent algorithms use spatial correlation as well as and temporal correlation in motion picture processing, the architecture can be shown to achieve efficient processing on these algorithms.
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Keyword(in English) parallel processor / signal processing / algorithm / low power
Paper # SIP2007-119,ICD2007-108,IE2007-78
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Conference Information
Committee SIP
Conference Date 2007/10/18(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Study on a TOPS scale architecture
Sub Title (in English)
Keyword(1) parallel processor
Keyword(2) signal processing
Keyword(3) algorithm
Keyword(4) low power
1st Author's Name Hiroshi SUZUKI
1st Author's Affiliation Tokyo Metropolitan University()
2nd Author's Name Takao NISHITANI
2nd Author's Affiliation Tokyo Metropolitan University
3rd Author's Name Bin Wu
3rd Author's Affiliation Tokyo Metropolitan University
4th Author's Name Hachiro FUJITA
4th Author's Affiliation Tokyo Metropolitan University
Date 2007-10-25
Paper # SIP2007-119,ICD2007-108,IE2007-78
Volume (vol) vol.107
Number (no) 285
Page pp.pp.-
#Pages 6
Date of Issue