| Presentation | 2007-10-25 New Compact and Power-Efficient Implementations of Rank-Order-Filters and Sorting Engines Using Time-Domain Computation Technique Liem T. NGUYEN, Kiyoto ITO, Tadashi SHIBATA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A compact and power-efficient digital implementation of rank order filters compatible with focal-plane image processing has been developed based on a time-domain computation technique. The magnitude of an analog pixel intensity is represented as a pulse width in the pulse width modulation scheme and the rank order filtering is accomplished using simple digital adders and a binary counter. As a result, a very compact implementation comparable to analog counterparts has been achieved, while preserving the accuracy and programmability of digital implementation, this enable us to use the rank order filter as a building block in a parallel processing array. A test chip capable of performing multiple rank order filtering for up to 16 inputs was designed and fabricated in a 0.35-μm standard CMOS technology. Experimental results have demonstrated the correct operation of the circuit in a low power dissipation (0.44mW at 3.3V) with a very compact core size (0.014mm^2). The circuit has shown the speed performance of over 260K ranks/s at 8-bit resolution, which is more than sufficient for use at typical video frame rates. In addition, a new architecture for compact implementation of sorting engines with some modification in peripheral circuitries of the proposed rank order filtering architecture is also presented. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | rank order filter / ROF / median filter / winner-take-all / sorting / parallel processing / hardware implementation |
| Paper # | SIP2007-117,ICD2007-106,IE2007-76 |
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| Conference Information | |
| Committee | SIP |
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| Conference Date | 2007/10/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Signal Processing (SIP) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | New Compact and Power-Efficient Implementations of Rank-Order-Filters and Sorting Engines Using Time-Domain Computation Technique |
| Sub Title (in English) | |
| Keyword(1) | rank order filter |
| Keyword(2) | ROF |
| Keyword(3) | median filter |
| Keyword(4) | winner-take-all |
| Keyword(5) | sorting |
| Keyword(6) | parallel processing |
| Keyword(7) | hardware implementation |
| 1st Author's Name | Liem T. NGUYEN |
| 1st Author's Affiliation | Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo() |
| 2nd Author's Name | Kiyoto ITO |
| 2nd Author's Affiliation | Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo |
| 3rd Author's Name | Tadashi SHIBATA |
| 3rd Author's Affiliation | Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo |
| Date | 2007-10-25 |
| Paper # | SIP2007-117,ICD2007-106,IE2007-76 |
| Volume (vol) | vol.107 |
| Number (no) | 285 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |