| Presentation | 2007-10-25 K-Means学習プロセッサシステムのためのマルチチップ・アーキテクチャ(システムLSIの応用と要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術及び一般) , |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For improvement of image recognition system, a K-means processor has been developed with gravity detection architecture aiming at real time compression of feature vectors generated from input images using a 0.18-μm 5metal CMOS technology. Because of the limit of chip dimension, this processor can only process 256 feature vectors. Since we need commonly to compute about 7000 vectors for general image analysis, We proposed a multiple-chip architecture for K-means learning processor systems to solve the scalability problem. In this paper, we expound the Multiple-Chip architecture base on formerly-developed K-means processor architecture and the prototype chip designed in 0.18um 5-metal CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | SIP2007-116,ICD2007-105,IE2007-75 |
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| Conference Information | |
| Committee | SIP |
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| Conference Date | 2007/10/18(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Signal Processing (SIP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
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| 1st Author's Affiliation | () |
| Date | 2007-10-25 |
| Paper # | SIP2007-116,ICD2007-105,IE2007-75 |
| Volume (vol) | vol.107 |
| Number (no) | 285 |
| Page | pp.pp.- |
| #Pages | 6 |
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