Presentation | 2007-10-25 Image Processing VLSI Architecture Based on Data Compression and Its Application Hisashi YOSHIDA, Yasuhiro KOBAYASHI, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | To design low-power and high-speed image processors, the reduction of the number of interconnection units plays an important role. This paper presents a data-compression-based VLSI architecture that reduces the number of interconnection units between processing elements and memory modules without performance degradation. For example of a stereo matching VLSI, the number of interconnection units is reduced to 25%. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Image Compression / Differential Encoding / Memory Architecture |
Paper # | SIP2007-111,ICD2007-100,IE2007-70 |
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Committee | SIP |
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Conference Date | 2007/10/18(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Signal Processing (SIP) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Image Processing VLSI Architecture Based on Data Compression and Its Application |
Sub Title (in English) | |
Keyword(1) | Image Compression |
Keyword(2) | Differential Encoding |
Keyword(3) | Memory Architecture |
1st Author's Name | Hisashi YOSHIDA |
1st Author's Affiliation | Graduate School of Infomation Sciences, Tohoku University() |
2nd Author's Name | Yasuhiro KOBAYASHI |
2nd Author's Affiliation | Oyama National College of Technology |
3rd Author's Name | Masanori HARIYAMA |
3rd Author's Affiliation | Graduate School of Infomation Sciences, Tohoku University |
4th Author's Name | Michitaka KAMEYAMA |
4th Author's Affiliation | Graduate School of Infomation Sciences, Tohoku University |
Date | 2007-10-25 |
Paper # | SIP2007-111,ICD2007-100,IE2007-70 |
Volume (vol) | vol.107 |
Number (no) | 285 |
Page | pp.pp.- |
#Pages | 4 |
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