Presentation	2007-10-25 A Study of Frame Buffer Cache Architecture Ryohei ISHIDA, Yoshiyuki KATO,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Frame buffer data, which is stored as two dimensional data, is accessed sequentially in both horizontal and vertical directions. When storing frame buffer data to cache memory, the cache memory should be accessible to the stored frame buffer data in both horizontal and vertical directions. General cache memory is supposed to store one dimensional data, so it is not always suitable for storing two dimensional data like frame buffer data. The purpose of this report is to propose a new cache memory architecture which is suitable for storing frame buffer data, and that utilizes the structure for two dimensional data.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Frame Buffer / Pixel Cache / Two dimensional data
Paper #	SIP2007-109,ICD2007-98,IE2007-68
Date of Issue

Conference Information
Committee	SIP
Conference Date	2007/10/18(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Signal Processing (SIP)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Study of Frame Buffer Cache Architecture
Sub Title (in English)
Keyword(1)	Frame Buffer
Keyword(2)	Pixel Cache
Keyword(3)	Two dimensional data
1st Author's Name	Ryohei ISHIDA
1st Author's Affiliation	Mitsubishi Electric Corporation Information Technology R&D Center()
2nd Author's Name	Yoshiyuki KATO
2nd Author's Affiliation	Mitsubishi Electric Corporation Information Technology R&D Center
Date	2007-10-25
Paper #	SIP2007-109,ICD2007-98,IE2007-68
Volume (vol)	vol.107
Number (no)	285
Page	pp.pp.-
#Pages	4
Date of Issue