Presentation 2007-10-16
Evaluation Model of Pseudo Random Pattern Quality for Logic BIST
Satoshi FUKUMOTO, Harunobu KUROKAWA, Masayuki ARAI, Kazuhiko IWASAKI,
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Abstract(in English) In this paper, we discuss the stochastic and statistical analyses on the distribution of fault coverage in random-pattern testing. We introduce the stochastic variable which maps the events of detection and non-detection of each fault on a random-pattern testing into the integers 1 and 0 respectively. Based on this stochastic variable, we establish the stochastic evaluation model and investigate the estimation of the distribution of fault coverage. We show that the expected number of detected faults and/or fault coverage can be estimated precisely from the test results for individual test patterns in one test sequence. We propose computational approach for nonparametric estimation of the distribution of fault coverage. Re-sampling from the results for individual test patterns in about 2 to 10 test sequences enables us to effectively generate the histogram for the distribution of fault coverage.
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Keyword(in English) built-in self test / linear feedback shift register / random pattern testing / fault coverage / re-sampling
Paper # DE2007-124,DC2007-21
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Committee DE
Conference Date 2007/10/8(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation Model of Pseudo Random Pattern Quality for Logic BIST
Sub Title (in English)
Keyword(1) built-in self test
Keyword(2) linear feedback shift register
Keyword(3) random pattern testing
Keyword(4) fault coverage
Keyword(5) re-sampling
1st Author's Name Satoshi FUKUMOTO
1st Author's Affiliation Faculty of System Design, Tokyo Metropolitan University()
2nd Author's Name Harunobu KUROKAWA
2nd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
3rd Author's Name Masayuki ARAI
3rd Author's Affiliation Faculty of System Design, Tokyo Metropolitan University
4th Author's Name Kazuhiko IWASAKI
4th Author's Affiliation Faculty of System Design, Tokyo Metropolitan University
Date 2007-10-16
Paper # DE2007-124,DC2007-21
Volume (vol) vol.107
Number (no) 254
Page pp.pp.-
#Pages 6
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