Presentation	2007-10-31 Technical Trends of Mismatch Modeling on Analog CMOS Circuit Hiroo MASUDA, Takeshi KIDA, Shin-ichi OHKAWA,
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Abstract(in English)	In sub-100-nm device, mismatch characteristics of threshold voltage and drain current have been degraded. This phenomenon causes variation of timing delay in digital SOC design. On the other hand, mixed signal LSI with analog circuits is expected to suffer from the mismatch-effects much compared with digital ones. This paper summarizes analog CMOS mismatch modeling activities and mismatch cancellation technique. We also report problems on mismatch design in future scaled low-voltage analog CMOS circuits.
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Keyword(in English)	Analog CMOS / Mismatch / Modeling / Trends
Paper #	VLD2007-69,SDM2007-213
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Conference Information
Committee	VLD
Conference Date	2007/10/24(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Technical Trends of Mismatch Modeling on Analog CMOS Circuit
Sub Title (in English)
Keyword(1)	Analog CMOS
Keyword(2)	Mismatch
Keyword(3)	Modeling
Keyword(4)	Trends
1st Author's Name	Hiroo MASUDA
1st Author's Affiliation	Renesas Technology Corp.()
2nd Author's Name	Takeshi KIDA
2nd Author's Affiliation	Renesas Technology Corp.
3rd Author's Name	Shin-ichi OHKAWA
3rd Author's Affiliation	Renesas Technology Corp.
Date	2007-10-31
Paper #	VLD2007-69,SDM2007-213
Volume (vol)	vol.107
Number (no)	296
Page	pp.pp.-
#Pages	8
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