Presentation 2007-09-21
Dynamically Reconfigurable Processor with Direct Execution Mode
Toru SANO, Yohei HASEGAWA, Satoshi TSUTSUMI, Hideharu AMANO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Multi-context dynamically reconfigurable processors require configuration data in the context memory to execute. It means that size of the context memory restricts size of an application. On the other hand, applications also contain sequntial codes which are not suitable for execution on dynamically reconfigurable processors. This paper proposes a dynamically reconfigurable processor with a direct execution mode. While executing in this mode, configuration data are not loaded from the context memory but an insturction buffer directly to improve the efficiency of the context memory. We added this mode to MuCCRA-1, which we have developed, and evaluated execution time and area overhead. As a result, although the execution time is more increased than that of the dynamically reconfigurable processor mode, it is much less than that of the MIPS CPU.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dynamically Reconfigurable Processor / Direct execution / SIMD
Paper # RECONF2007-29
Date of Issue

Conference Information
Committee RECONF
Conference Date 2007/9/13(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dynamically Reconfigurable Processor with Direct Execution Mode
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) Direct execution
Keyword(3) SIMD
1st Author's Name Toru SANO
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Yohei HASEGAWA
2nd Author's Affiliation Faculty of Science and Technology, Keio University
3rd Author's Name Satoshi TSUTSUMI
3rd Author's Affiliation Faculty of Science and Technology, Keio University
4th Author's Name Hideharu AMANO
4th Author's Affiliation Faculty of Science and Technology, Keio University
Date 2007-09-21
Paper # RECONF2007-29
Volume (vol) vol.107
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue