Presentation | 2007-09-21 Pipeline MD5 Implementations on FPGA with Data Forwarding Anh Tuan HOANG, Katsuhiro YAMAZAKI, Shigeru OYANAGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The hash algorithm or message digest algorithm such as SHA and MD5 are used to generate a unique message digest for an arbitrary message. This paper describes 3 stages pipeline MD5 implementations on FPGA. This work removes the data dependency of a single step inside the main loop of the MD5 algorithm by data forwarding methodology, and breaks the computation into 3 pipeline stages. Two implementations without/with BRAM are given. They occupy 1010 and 885 hardware slices on Xilinx Vertex-II XC2V4000-6 FPGA chip, and achieve 700 Mbps and 746 Mbps, respectively. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | MD5 algorithm / Pipeline / Data dependency / Data forwarding / FPGA / BRAM |
Paper # | RECONF2007-27 |
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Committee | RECONF |
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Conference Date | 2007/9/13(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Pipeline MD5 Implementations on FPGA with Data Forwarding |
Sub Title (in English) | |
Keyword(1) | MD5 algorithm |
Keyword(2) | Pipeline |
Keyword(3) | Data dependency |
Keyword(4) | Data forwarding |
Keyword(5) | FPGA |
Keyword(6) | BRAM |
1st Author's Name | Anh Tuan HOANG |
1st Author's Affiliation | Department of VLSI System Design, Ritsumeikan University() |
2nd Author's Name | Katsuhiro YAMAZAKI |
2nd Author's Affiliation | Department of VLSI System Design, Ritsumeikan University |
3rd Author's Name | Shigeru OYANAGI |
3rd Author's Affiliation | Department of Computer Science, Ritsumeikan University |
Date | 2007-09-21 |
Paper # | RECONF2007-27 |
Volume (vol) | vol.107 |
Number (no) | 225 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |