| Presentation | 2007-09-21 A Study on Multibyte Processing for NFA-based Pattern Matching Circuits Norio YAMAGAKI, Satoshi KAMIYA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, some studies about NFA (Non-deterministic Finite Automaton) implementation in logic have been undertaken to achieve high-speed pattern matching. In such NFA-based pattern matching circuits, NFA logic is placed directly into a reconfigurable hardware device like FPGA. In particular, both search throughput and logic size are important features because it is assumed that this kind of pattern matching hardware is used in systems requiring high-speed operation, such as NIDS (Network Intrusion Detection System). In this paper, a generation method of NFA with multibyte transitions without increasing the number of states is proposed in order to address the above issues. This proposed method can transform NFA with 1-byte transitions into one with multibyte transitions by using matrix operations. In addition, this method enables to improve search throughput according to the number of processing bytes and to reduce its logic size by constraining the register utilization. Moreover, this paper shows the results of performance evaluations by implementing generated NFA into FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NFA / Pattern Matching / Multibyte Processing / FPGA |
| Paper # | RECONF2007-26 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/9/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Multibyte Processing for NFA-based Pattern Matching Circuits |
| Sub Title (in English) | |
| Keyword(1) | NFA |
| Keyword(2) | Pattern Matching |
| Keyword(3) | Multibyte Processing |
| Keyword(4) | FPGA |
| 1st Author's Name | Norio YAMAGAKI |
| 1st Author's Affiliation | System IP Core Research Laboratories, NEC Corporation() |
| 2nd Author's Name | Satoshi KAMIYA |
| 2nd Author's Affiliation | System IP Core Research Laboratories, NEC Corporation |
| Date | 2007-09-21 |
| Paper # | RECONF2007-26 |
| Volume (vol) | vol.107 |
| Number (no) | 225 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |