| Presentation | 2007-09-21 Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs Yuji ISHIKAWA, Satoshi KOMATSU, Masahiro FUJITA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Protocol transducer synthesis is one of the most important issues for efficient IP core reuse in SoC designs. We proposed an automatic protocol transducer synthesis method in [1], [2]. In this paper, we propose an application of our protocol synthesis method to reconfigurable architecture on FPGA that enables to utilize various IPs dynamically. In coarsegrained reconfigurable architectures such as hardware OS, protocol transducers should also be dynamically reconfigured to make the dynamically loaded IPs able to communicate with one another. In our proposed method, a protocol transducers is synthesized as set of partial-transducers at design time. A whole transducer is also constructed at runtime, by selecting and placing partial transducers dynamically. The proposed method contributes to the improvement of area efficiency by constructing minimum transducers. Each partial transducer can be given in either layouted design hard macros or in netlists. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | protocol transducer / dynamic reconfiguration / design reuse |
| Paper # | RECONF2007-24 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/9/13(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs |
| Sub Title (in English) | |
| Keyword(1) | protocol transducer |
| Keyword(2) | dynamic reconfiguration |
| Keyword(3) | design reuse |
| 1st Author's Name | Yuji ISHIKAWA |
| 1st Author's Affiliation | Department of Electronics Engineering, School of Engineering, University of Tokyo() |
| 2nd Author's Name | Satoshi KOMATSU |
| 2nd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 3rd Author's Name | Masahiro FUJITA |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 2007-09-21 |
| Paper # | RECONF2007-24 |
| Volume (vol) | vol.107 |
| Number (no) | 225 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |