Presentation 2007-09-21
Hardware/Software Partitioning for SoPC based Embedded Systems
Kenichi SHIMADA, Masaru FUKUSHI, Susumu HORIGUCHI,
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Abstract(in English) This paper proposes a novel hardware/software partitioning model for SoPC (System on a Programmable Chip) based embedded systems. Considering the property that the function of a soft processor is customizable in SoPC, our proposed model introduces custom instruction as a new context of hardware implementation. This model allows to generate efficient embedded systems in terms of chip area and processing time. For large scale embedded systems, we also propose a fast partitioning method based on a priority order. It is demonstrated on several benchmarks that the proposed model generates faster and smaller systems than the previous model.
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Keyword(in English) Embedded System Design / Hardware/Software Partitioning / SoPC / Soft Processor / Custom Instruction
Paper # RECONF2007-23
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Committee RECONF
Conference Date 2007/9/13(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware/Software Partitioning for SoPC based Embedded Systems
Sub Title (in English)
Keyword(1) Embedded System Design
Keyword(2) Hardware/Software Partitioning
Keyword(3) SoPC
Keyword(4) Soft Processor
Keyword(5) Custom Instruction
1st Author's Name Kenichi SHIMADA
1st Author's Affiliation System ASIC Division, NEC Electronics Corporation()
2nd Author's Name Masaru FUKUSHI
2nd Author's Affiliation Graduate School of Information Science, Tohoku University
3rd Author's Name Susumu HORIGUCHI
3rd Author's Affiliation Graduate School of Information Science, Tohoku University
Date 2007-09-21
Paper # RECONF2007-23
Volume (vol) vol.107
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue