Presentation 2007-09-21
A Study of Performance-driven Simultaneous Clustering and Placement for FPGA
Hiroshi SHINOHARA, Masahiro IIDA, Toshinori SUEYOSHI,
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Abstract(in English) FPGA has a rich flexibility to emulate various circuits, and their performance depend on design tools. In this paper, we present a design technique for area reduction intended for clustered FPGAs. In order to improve routability, this technique processes clustering and placing simultaneously and iteratively. As compared to exsisting routability-driven clustering approach, our technique show equivalent efficacy for area and delay optimization in a shorter process time. And it has a room for delay improvement as long as it leverages local interconnection in Logic Blocks.
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Keyword(in English) FPGA / Clustering / Placing / Simultaneous Optimization / Routability-Driven
Paper # RECONF2007-22
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Committee RECONF
Conference Date 2007/9/13(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study of Performance-driven Simultaneous Clustering and Placement for FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Clustering
Keyword(3) Placing
Keyword(4) Simultaneous Optimization
Keyword(5) Routability-Driven
1st Author's Name Hiroshi SHINOHARA
1st Author's Affiliation Department of Computer Science, Kumamoto University()
2nd Author's Name Masahiro IIDA
2nd Author's Affiliation Department of Computer Science, Kumamoto University
3rd Author's Name Toshinori SUEYOSHI
3rd Author's Affiliation Department of Computer Science, Kumamoto University
Date 2007-09-21
Paper # RECONF2007-22
Volume (vol) vol.107
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue